MYSP-PI-2022-078

余成斌


下載導師簡歷CV
Section 1: Personal Particulars

余成斌
U Seng Pan
Professor
66678233
ben.u@akrostar-tech.com
澳门冼星海大马路 金龙中心 6楼C-G座
芯耀辉科技有限公司
芯耀辉科技有限公司
联席CEO兼澳门董事总经理

Research Project provided for Macao Youth Scholars Program:

于先进CMOS工艺的高速SerDes之模拟与混合信号集成电路设计
Analog & Mixed-Signal IC Design for High Speed SerDes at Advanced CMOS Technology
0809 电子科学与技术
0810 信息与通信工程
Practical experience in Analog & Mixed-Signal IC Design, preferable with high-speed SerDes design experience
PhD
See CV

Section 2: Research Interests and Grants

CMOS Analog IC Design, Switched-Capacitor Circuits Design, High-Performance Data-Converter Design, Analog Front-End for Communication & Consumer Electronic SoC, SerDes and Wireline ICs
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11
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高速接口IP研发, 珠海横琴新区管理委员会 1亿人民币,5年